The present disclosure relates to semiconductor device fabrication. More particularly, the present disclosure relates to methods of forming well-controlled junction butting in semiconductor-on-insulator field effect transistors with an embedded source and an embedded drain.
Embedded source/drain techniques have been widely used to improve charge carrier mobility as channel lengths of semiconductor-on-insulator (SOI) field effect transistors (FETs) are scaled down to the sub-50-nm range. Embedded source/drain techniques typically include removing the source region and the drain region that are present in a semiconductor substrate to form trenches followed by epitaxially growing a semiconductor material in the trenches.
SOI FETs with an embedded source region and an embedded drain region (collectively referred to herein after as “embedded source/drain regions”) require junction butting to ensure low junction capacitance and to avoid cross-talk between adjacent FETs. To provide adequate junction butting, ion implantation of appropriate dopants through the bottom of the trenches is typically performed. However, the trenches do not provide any control over the lateral placement and spread of implanted dopants. Subsequent thermal cycles diffuse the implanted dopants to the channel regions of SOI FETs, creating undesired effects, such as short channel effects and low backside threshold voltage, which in turn result in backside conduction. As such, there remains a need to develop methods that can provide better control over the junction butting in SOI FETs with embedded source/drain regions.